During a fabrication process of a high density multi-layered semiconductor device, one of the most important processing steps is planarizing a layer of a semiconductor wafer by removing uneven topographic features of the wafer. The layer planarization allows patterns that are subsequently formed above that layer to be more uniform. In the case of conductive patterns, the planarization of the underlying layer reduces the probability of electrical shorts between the conductive patterns, which is a growing concern as the density of microelectronic circuitry included in a semiconductor device is progressively increased.
Chemical mechanical polishing (CMP) is a well-accepted technique to planarize a layer of a semiconductor wafer during the fabrication process by chemically and mechanically removing uneven topographic features of the wafer. A conventional CMP technique involves polishing the surface of a wafer with a rotating polishing pad using a slurry of colloidal particles in an aqueous solution. The slurry promotes planarization of the wafer surface by producing a chemical reaction with the wafer surface and by providing abrasives to “grind” the wafer surface with the polishing pad.
A common conventional CMP system utilizes a single polishing pad to polish one semiconductor wafer at a time. However, CMP systems have been developed that can simultaneously polish multiple semiconductor wafers on one or more polishing pads to increase throughput. U.S. Pat. No. 5,498,199 to Karlsrud et al. describes a CMP apparatus that utilizes a multi-head wafer polish assembly with five wafer carriers to simultaneously polish five multiple semiconductor wafers on a single large polishing pad. In operation, five semiconductor wafers are sequentially placed on five loading cups of an index table, which is situated adjacent to the polishing pad. When all of the semiconductor wafers are in place, the loading cups are raised to attach the wafers onto the wafer carriers of the multi-head wafer polish assembly, which are positioned over the loading cups. The multi-head wafer polish assembly is then moved to the polishing pad, where all five semiconductor wafers are polished on the polishing pad. After the polishing, the multi-head wafer polish assembly is transferred back to the index table, where the polished semiconductor wafers are placed on five unloading cups of the index table. The loading cups and the unloading cups are situated on the index table in an alternating fashion, forming is a circle of ten loading/unloading cups. The polished semiconductor wafers are then sequentially unloaded from the unloading cups.
A disadvantage of the CMP apparatus of Karlsrud et al. is that a significant amount of time is required to sequentially load new semiconductor wafers onto the loading cups before the wafers can be polished. During this period, the polishing pad remains idle. In addition, similar amount of time is required to sequentially unload polished semiconductor wafers from the unloading cups. Thus, the polishing process of the CMP apparatus of Karlsrud et al. includes substantial idle periods, which potentially decreases the throughput of the apparatus. Furthermore, the index table of the loading and unloading cups occupies a significant amount of space, which increases the footprint of the CMP apparatus.
U.S. Pat. No. 5,738,574 to Tolles et al. describes a CMP apparatus that can simultaneously polish three semiconductor wafers using multiple polishing pads. The CMP apparatus of Tolles et al. includes three polishing stations and a wafer transfer station, which are located at different quadrants about a rotational axis. Each polishing station includes a single polishing pad to polish a semiconductor wafer. The apparatus also includes four wafer carriers that are suspended from a carousel. The carousel is configured to rotate the wafer carriers such that each wafer carrier can be sequentially positioned at each of the four stations. In operation, the three semiconductor wafers on the wafer carriers positioned at the three polishing stations are polished by the polishing pads at the polishing stations. During this period, the semiconductor wafer on the wafer carrier positioned at the wafer transfer station is unloaded and a new semiconductor wafer is loaded onto that wafer carrier. After a predefined polishing period, the wafer carriers are rotated such that each wafer carrier is positioned at a subsequent station. Once the wafer carriers are properly positioned, the three semiconductor wafers at the polishing stations are polished, while the fourth semiconductor wafer at the transfer station is unloaded and a new semiconductor loaded. In this fashion, semiconductor wafers can be continuously processed by the apparatus such that each semiconductor wafer is sequentially polished at the three polishing stations.
Another CMP apparatus that can simultaneously polish multiple semiconductor wafers using multiple polishing pads is described in U.S. Pat. No. 6,136,715 to Shendon et al. The CMP apparatus of Shendon et al. includes a first polishing station, a second polishing station and a wafer transfer station. The first polishing station includes a large polishing pad, while the second polishing station includes a smaller polishing pad. The apparatus also includes multiple wafer carriers that are suspended from a rotatable carousel. In one embodiment, the apparatus includes four wafer carriers. The carousel is configured to rotate the wafer carriers such that each wafer carrier can be sequentially positioned at four locations. Two of the four locations coincide with the transfer station and the second polishing station. The remaining two locations are both at the first polishing station. In operation, the three semiconductor wafers on the wafer carriers positioned at the two polishing stations are polished by the two polishing pads at the polishing stations. Thus, two wafers are polished at the first polishing station. During this period, the semiconductor wafer on the wafer carrier positioned at the wafer transfer station is unloaded and a new semiconductor wafer is loaded onto that wafer carrier. After a predefined polishing period, the wafer carriers are rotated such that each wafer carrier is positioned at a subsequent location. Once the wafer carriers are properly positioned, the three semiconductor wafers at the polishing stations are polished, while the fourth semiconductor wafer at the transfer station is unloaded and a new semiconductor loaded. This cycle is repeated to sequentially polishing additional semiconductor wafers.
A concern with the above-described CMP apparatuses with multiple polishing pads is that the time required to unload a polished semiconductor wafer and then to load a new semiconductor wafer at the wafer transfer station is typically shorter in duration than the polishing time at the polishing stations. Thus, the new semiconductor wafer must remain idle until end of the polishing time. Consequently, valuable processing time is wasted at the transfer station for each semiconductor wafer to be polished.
Another concern with the above-described CMP apparatuses with multiple polishing pads is that the footprint tends to be large due to the use of multiple polishing pads. The size of the polishing pads depends on the size of the semiconductor wafers being polished. Thus, the concern of increased footprint is more significant when polishing 300 μm or larger semiconductor wafers.
Another concern with the above-described CMP apparatuses with multiple polishing pads is that the difficult task of pad conditioning to ensure proper pad profile is compounded by the use of multiple polishing pads.
In view of the above concerns, there is a need for an apparatus and method for chemically and mechanically polishing semiconductor wafers that provides increased efficiency and reduced footprint for the apparatus.